Multilayer substrates have conventionally been indispensable components as substrates to mount thereon electronic components used in electronic devices and in precision instruments such as measuring devices. Since these electronic devices and precision instruments are used under various environments from a low-temperature environment to a high-temperature environment, the multilayer substrates need to have weather resistance according to the various environments. For example, as shown in FIG. 8, a multilayer substrate 1 has a base layer 2, a surface layer 3, and a plurality of electrodes 4. When the multilayer substrate 2 is exposed to a high-temperature environment in a case where the surface layer 3 has a larger coefficient of thermal expansion than that of the base layer 2, the surface layer 3 expands to a larger extent than the base layer 2, so that the multilayer substrate 1 bends as shown by the arrow in the drawing. Though FIG. 8 shows both the base layer 2 and the surface layer 3 as a single layer, the base layer 2 of the multilayer substrate 1 is generally structured as a multilayer substrate composed of a plurality of layers.
In a case of a probe device which inspects electrical characteristics of devices in a semiconductor manufacturing field, since the probe device conducts low-temperature tests and high-temperature tests according to the environments where the devices are used, a circuit board used for the probe device is liable to be thermally deformed due to the influence of temperature. In particular, a multilayer substrate used for the probe card is directly exposed to a low-temperature environment or a high-temperature environment and thus is especially greatly influenced by temperature.
A probe device includes, for example, as shown in FIG. 9(a), a loader chamber 1 for transferring a wafer W and a prober chamber 2 in which electrical characteristics of the wafer W delivered from the loader chamber 1 are inspected. As shown in FIG. 9(a), the prober chamber 2 includes: a mounting table (main chuck) 3 on which the wafer W carried from the loader chamber 1 is placed and which is provided with a built-in lifting mechanism; an XY table 4 for moving the main chuck 3 in an X direction and a Y direction; a probe card 5 disposed above the main chuck 3 moved by the XY table; a card holding mechanism (hereinafter, referred to as a “clamp mechanism”, not shown) holding the probe card 5 in an attachable/detachable manner; and an alignment mechanism 6 accurately aligning a plurality of probes 5A of the probe card 5 with a plurality of electrode pads of the wafer W on the main chuck 3. The alignment mechanism 6 includes an upper camera 6A capturing an image of the wafer W and a lower camera 6B capturing images of the probes 5A.
Further, as shown in FIG. 9(a), a head plate 7 is disposed on an upper surface of the prober chamber 2, and the clamp mechanism holding the probe card 5 in the attachable/detachable manner is fitted in an opening portion of the head plate 7. A test head T of a tester (not shown) is rotatably disposed on the head plate 7, and the test head T and the probe card S are electrically connected to each other via a connection ring (pogo ring) 8. The tester transmits inspection signals to the probes 5A via the test head T, a performance board, and the pogo ring 8, and the probes 5A apply the inspection signals to the electrode pads of the wafer W, thereby inspecting the electrical characteristics of a plurality of semiconductor elements (devices) formed on the wafer W.
In a case where a circuit board 5B included in the probe card S includes, for example, as shown in FIG. 9(b): a base layer 5C made of an inorganic insulating material such as glass fiber; surface layers 5D stacked on both surfaces of the base layer 5C and made of an organic insulating material such as resin; and electrodes 5E, the surface layer 5D on a main chuck 3 side (lower side in the drawing) becomes higher in temperature than the surface layer 5D on a pogo ring 8 side (upper side in the drawing) to greatly expand at the time of high-temperature inspection, and consequently, the circuit board 5B bends in the arrow direction to cause misalignment of the electrodes 5E with pogo pins of the pogo ring 8, which may possibly deteriorate reliability of the inspection.
In view of the above, Patent document 1 proposes a jig for semiconductor device inspection (pin probe-type jig small in thermal deformation). The jig for semiconductor device inspection described in Patent document 1 is composed of a probe and a multilayer printed wiring board, and the multilayer printed wiring board includes a conductor circuit 1 having a terminal connected to at least the probe, a conductor circuit 2 having a terminal connected to an inspection device, two or more layers of electric insulating layers supporting these circuit conductor layers, and a through hole electrically connecting these circuit conductor layers, and a coefficient of thermal expansion in a planar direction of the electric insulating layer supporting the conductor circuit 1 is smaller than a coefficient of thermal expansion in the planar direction of the electric insulating layer supporting the conductor circuit 2.
[Patent document 1] Japanese Patent Application Laid-open No. Hei 9-133710